This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-198978, filed Jul. 13, 1999; and No. 2000-208341, filed Jul. 10, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor memory and, more particularly, to an Ferroelectric Random Access Memory (Ferroelectric RAM).
An Ferroelectric RAM is a semiconductor memory that uses a ferroelectric film as part of a memory cell. The polarization state of this ferroelectric film determines the data (xe2x80x9c0xe2x80x9dor xe2x80x9c1xe2x80x9d) in the memory cell. The Ferroelectric RAM has many characteristic features, e.g., capabilities of performing high-speed operation, reducing power consumption, increasing memory capacity, and increasing the allowable number of re-write operations (write/erase cycles), and nonvolatility, i.e., retaining data in the absence of power.
Presently, as memory cells for the Ferroelectric RAM, a memory cell obtained by replacing the capacitor insulating film of a memory cell for a DRAM (Dynamic Random Access Memory) with a ferroelectric film, a memory cell obtained by replacing the gate insulating film of a MISFET (Metal Insulated Semiconductor Field Effect Transistor) with a ferroelectric film, and the like are known.
A memory cell having a structure obtained by replacing the gate insulating film of a MISFET with a ferroelectric film is called an MFSFET (Metal-Ferroelectric-Semiconductor Field Effect Transistor). The MFSFET implements a memory function by controlling a current flowing between the source region and the drain region in accordance with the polarization state of the ferroelectric film (assume that polarization which is positive on the substrate side and negative on the gate electrode side is under-direction polarization, and polarization which is negative on the substrate side and positive on the gate electrode side is upper-direction polarization).
In comparison with a memory cell obtained by replacing the capacitor insulating film of a DRAM with a ferroelectric film, an MFSFET allows a reduction in cell size based on the scaling law, and hence suited to achieving an increase in memory capacity and a reduction in chip area. In addition, the MFSFET has an excellent feature that it allows nondestructive data read operation. On the other hand, the MFSFET has its unique technical problems for practical use, e.g., a problem in the process of forming a ferroelectric film on a semiconductor substrate (silicon substrate) (interdiffusion of atoms or the relative dielectric constant of a buffer layer when it is used).
For example, the following are presently known as research papers on the Ferroelectric RAM having MFSFETs:
reference 1: H. Ishihara et al., xe2x80x9cProposal of a Single-Transistor-Cell-Type Ferroelectric Memory Using an SOI structure and Experimental Study on the Interference Problem in the Write Operationxe2x80x9d Jpn J. Appl. Phys. Vol. 36, pp. 1655-1658, Mar. 1997,
reference 2: Hiroshi Ishihara, xe2x80x9cFabrication of ferroelectric-gate FETs and their application to neural networksxe2x80x9d OYO BUTURI, Vol. 66, No. 12, pp. 1335-1339 (1997), and
reference 3: Hiroshi Ishihara, xe2x80x9cCurrent state of Ferroelectric-gate FETs and their problemsxe2x80x9d, Technical Report of IEICE ED97-213, pp. 9-16, Mar. 1998.
A prototype technique for the current MFSFETs is disclosed in the patent application filed by Bell Telephone Laboratories (W. L. Brown, U.S. Pat. No. 2,791,759, I. M. Ross, U.S. Pat. No. 2,791,760) in 1955.
Ever since the proposal of this technique, research and development on MFSFETs have been intermittently conducted over 40-odd years. With regard to MFSFETs, however, unique technical problems which are difficult to solve, the challenge of obtaining excellent interface characteristics by preventing interdiffusion of atoms between a ferroelectric film and a semiconductor film (silicon film), in particular, have not been satisfactorily solved. Currently, therefore, MFSFETs have not reached a level at which they can be put into practical use.
Recently, in order to cope with increases in speed and complexity of electronic devices, there have been strong user demands for semiconductor memories which can realize faster operation, over power consumption, larger memory capacity, a larger allowable number of re-write operations, nonvolatility, and the like. Under the circumstances, a great deal of attention has been paid to the Ferroelectric RAM which can meet such demands, and research and development on the Ferroelectric RAM having MFSFETs have been vigorously conducted mainly in Japan and Korea.
A prototype of an Ferroelectric RAM has a so-called simple matrix structure in which stripe electrodes extending in the Y-direction are arranged below a ferroelectric film, and stripe electrodes extending in the X-direction are arranged on the ferroelectric film. In this structure, however, in program operation, a voltage is partly applied to unselected cells other than a selected cell. For this reason, repetitive write operation causes an interference effect, i.e., inversion of the data an unselected cells.
In order to prevent this interference effect, therefore, research and development have currently been conducted on an Ferroelectric RAM having an active matrix structure using FETs for cell selection, an Ferroelectric RAM as an improvement of an Ferroelectric RAM having a simple matrix structure, and the like.
FIG. 1 shows an embodiment of the conventional cell array arrangement of an Ferroelectric RAM using MFSFETs. FIG. 2 is an equivalent circuit of the device in FIG. 1.
This Ferroelectric RAM is disclosed in reference 3 and has a simple matrix structure.
A silicon oxide film (SiO2) 12 is formed on a silicon substrate 11. For example, striped silicon films 13 extending in the Y-direction are formed on the silicon oxide film 12. Each silicon film 13 has a p-type region and two n-type regions sandwiching the p-type region. The silicon substrate 11, silicon oxide film 12, and silicon film 13 constitute an SOI (Silicon On Insulator) structure.
Ferroelectric films 14 are formed on the silicon films 13 to completely cover the silicon films 13.
Striped metal films (gate electrodes) 15 extending in the X-direction are formed on the ferroelectric films 14. The silicon films (silicon stripes) 13 and metal films (metal stripes) 15 are arranged to intersect at right angles, thereby forming a simple matrix structure. MFSFETs 16 are formed at the intersections of the silicon films 13 and metal films 15.
In the cell array structure, plural memory cells formed in one silicon stripe are connected in parallel with each other and share one source region and one drain region. For this reason, there is no need to form contact holes for the source and drain regions in each memory cell, and hence this structure is suited to increasing the packing density of memory cells.
The basic operation of the Ferroelectric RAM shown in FIGS. 1 and 2 will be described next.
For the sake of descriptive convenience, assume that in the following description, an electric field generated in the ferroelectric film when a low potential is applied to the silicon film 13 and a high potential is applied to the metal film 15 is defined as an under-direction electric field, and an electric field generated in the ferroelectric film when a high potential is applied to the silicon film 13, and a low potential is applied to the metal film 15 is an upper-direction electric field. In addition, assume that polarization which is positive on the silicon film side and negative on the metal film side is under-direction polarization, and polarization which is negative on the silicon film side and positive on the metal film side is upper-direction polarization. Furthermore, assume that under-direction polarization (remanent polarization point) corresponds to a xe2x80x9c1xe2x80x9d-state (xe2x80x9c1xe2x80x9d-programming state), and upper-direction polarization (remanent polarization point) corresponds to a xe2x80x9c0xe2x80x9d-state (xe2x80x9c0xe2x80x9d-programming state or erase state).
(1) Program Operation
First of all, initialization is performed. In initialization, Vp is applied to all the silicon films (silicon stripes) 13, and 0V is applied to all the metal films (metal stripes) 15. At this time, upper-direction polarization is generated in the ferroelectric films 14 (limited to the portions where the silicon stripes and metal stripes cross each other; ditto for the following description) of all the memory cells.
As shown in FIG. 3, in the ferroelectric film 14 to which no electric field has been applied, the polarization state moves from a point A to a point B.
In the ferroelectric film 14 in which a xe2x80x9c0xe2x80x9d-state is stored, the polarization state moves from a point C to the point B. In the ferroelectric film 14 in which a xe2x80x9c1xe2x80x9d-state is stored, the polarization state moves from a point E to the point B through a point G (polarization inversion). That is, the ferroelectric films 14 of all memory cells have upper-direction polarization. Each polarization value is a saturated polarization value Pmax.
When the potential applied to each silicon film 13 is changed from Vp to 0V, the electric field in the ferroelectric film 14 of each memory cell becomes 0, and the amount of upper-direction polarization in the ferroelectric film 14 does not becomes 0 but becomes a remanent polarization value Pr (point C=remanent polarization point). That is, all the memory cells are initialized to the xe2x80x9c0xe2x80x9d-state (in which the threshold value is high) (see FIG. 4).
Subsequently, xe2x80x9c1xe2x80x9d-programming is performed for a selected memory cell. More specifically, Vp is applied to the selected metal stripe; Vp/3, to each unselected metal stripe; 0V, to the selected silicon stripe; and 2Vp/3, to each unselected silicon stripe.
At this time, as shown in FIG. 6, the voltage (potential difference) Vp is applied to the ferroelectric film of the selected memory cell (indicated by ⊚), and an under-direction electric field is generated in the ferroelectric film. This under-direction electric field has a value sufficient for inversion of the polarization in the ferroelectric film of the selected memory cell from upper-direction polarization to under-direction polarization, i.e., polarization inversion of the ferroelectric film. Therefore, the polarization state of the ferroelectric film of the selected memory cell moves from a point C to a point F and a point D, and the polarization value of under-direction polarization in the ferroelectric film becomes a saturated polarization value -Pmax.
Meanwhile, a voltage +Vp/3 or xe2x88x92Vp/3 is applied to the ferroelectric films of all unselected memory cells (indicated by white and black circles) other than the selected memory cell.
An under-direction electric field is generated in the ferroelectric film to which the voltage +Vp/3 is applied. This under-direction electric field does not have a value sufficient for inversion of the polarization in the ferroelectric film of the unselected memory cell from upper-direction polarization to under-direction polarization, i.e., polarization inversion of the ferroelectric film. Therefore, the polarization state of the ferroelectric film to which the voltage +Vp/3 is applied is between the point C and the point F, and the polarization of the ferroelectric film is kept in the upper direction.
An upper-direction electric field is generated in the ferroelectric film to which the voltage xe2x88x92Vp/3 is applied. Therefore, the polarization state of the ferroelectric film to which the voltage xe2x88x92Vp/3 is applied is between the point C and the point B. The polarization of the ferroelectric film is kept in the upper direction.
When all silicon films 13 and metal films 15 are set to 0V thereafter, the polarization state of the selected memory cell is set in the xe2x80x9c1xe2x80x9d-state (in which the threshold value is low) because the polarization state changes from the point D to the point E (remanent polarization point) (see FIG. 5). Meanwhile, the polarization state of each unselected memory cell is restored to the point C (remanent polarization point), and hence the unselected memory cell maintains the xe2x80x9c0xe2x80x9d-state (see FIG. 4).
In the above program operation, 0V is applied to the selected silicon film 13, and 2Vp/3 is applied to each unselected silicon film 13. At this time, since plural silicon films (silicon stripes) 13 are physically spaced apart from each other, sufficient insulation properties are ensured between the adjacent memory cells as compared with a well isolation process of forming plural wells in one silicon film.
Alternatively, as shown in FIG. 7, predetermined potentials may be applied to the silicon films 13 and metal films 15 after the above program operation. In this case, since a voltage that is equal in magnitude and opposite in direction to the voltage applied in the program operation is applied to the ferroelectric films 14 of most memory cells, an interference effect can be effectively reduced.
(2) Read Operation
In a memory cell (n-channel MFSFET) in the xe2x80x9c1xe2x80x9d-state, negative charge is induced on the surface of the channel, i.e., the surface of the p-type region of the silicon film 13, by the under-direction remanent polarization in the ferroelectric film 14. Therefore, the threshold value of the memory cell in the xe2x80x9c1xe2x80x9d-state is smaller than that of a memory cell in the xe2x80x9c0xe2x80x9d-state .
In a memory cell (n-channel MFSFET) in the xe2x80x9c0xe2x80x9d-state, positive charge is induced on the surface of the channel, i.e., the channel of the p-type region of the silicon film 13, by the upper-direction remanent polarization in t he ferroelectric film 14. Therefore, the threshold value of the memory cell in the xe2x80x9c0xe2x80x9d-state is larger than that of the memory cell in the xe2x80x9c1xe2x80x9d-state.
As shown in FIG. 8, therefore, a predetermined read potential Vread is set, at which a drain current Id flows in the memory cell in the xe2x80x9c1xe2x80x9d-state, but no drain current Id flows in the memory cell in the xe2x80x9c0xe2x80x9d-state, and the read potential Vread is applied to the selected metal film (metal stripe) 15. The read operation is then completed by checking whether a cell current flows in the select ed memory cell.
Assume that when 103 memory cells are connected in parallel in a silicon stripe, and 0V is applied to each unselected metal film 15, a leak current Ileak is produced in each unselected memory cell in the silicon stripe. In this case, in order to perform an accurate read, the read current (drain current Id) must be at least about 104 times the leak current Ileak.
Assume that about 0.1V is required to increase a current in the sub-threshold region of an FET by one order of magnitude. In this case, the read potential Vread is about 0.4V.
FIG. 9 is a plan view showing the cell array structure of the Ferroelectric RAM disclosed in references 1 to 3. FIG. 10 is a sectional view taken along a line Xxe2x80x94X in FIG. 9.
As described above, memory cells are formed at the intersections of silicon stripes and metal stripes. In each silicon stripe, a p-type region (channel) and two n-type regions (source and drain) sandwiching the p-type region are formed. Each metal stripe serves as a word line. The silicon stripes are physically isolated from each other and spaced a predetermined distance apart from each other.
A cell size in the use of such a cell array structure will be examined below.
Assume that the interval between the silicon stripes (element isolation width) is F (Feature size representing the minimum value of a design rule). In this case, the size of each memory cell in the X-direction (or bit line pitch) is 4F, and the size of each memory cell in the Y-direction (or word line pitch) is 2F. Therefore, the size of one memory cell is 8F2 (=4Fxc3x972F).
This memory cell size is larger than the cell size of a nonvolatile semiconductor memory such as a flash memory. For example, in a NAND flash EEPROM having a NAND string consisting of 16 series-connected memory cells, the size of one memory cell is 4.5F2 (to be described in detail later). If, therefore, an Ferroelectric RAM having a large memory capacity is to be manufactured, the chip size becomes large, resulting in a decrease in yield and an increase in cost. In addition, the Ferroelectric RAM having the cell array structure described above requires a decoder for controlling a potential to be applied to each silicon stripe in data re-write operation (overwrite operation), i.e., cell data change operation, resulting in an increase in complexity of a control circuit and an increase in chip size.
The present invention relates to a semiconductor memory that allows a high-density cell layout.
A nonvolatile semiconductor memory (EEPROM) in which digital bit data is stored as a charge amount in a floating gate electrode is known well.
In this nonvolatile semiconductor memory, charge is injected from a channel into a floating gate electrode through a tunnel insulating film, and is extracted from the floating gate electrode to the channel through the tunnel insulating film. A current flowing in the tunnel insulating film upon movement of the charge is called a tunnel current.
The digital bit data stored in the memory cell can be read out from the memory cell by measuring the charge amount in the floating gate electrode as the change amount of conductance of the memory cell (MOSFET).
Of the nonvolatile semiconductor memories under research and development, a NAND EEPROM or AND EEPROM can greatly decrease the number of select gate transistors as compared with the number of memory cells, and hence is suited to increasing the packing density of memory cells.
As is known, a NAND EEPROM has a cell unit in which plural memory cells are connected in series with each other, thereby realizing a high packing density of memory cells. In addition, as is known, an AND EEPROM has a cell unit in which plural memory cells are connected in parallel with each other, thereby realizing a high packing density of memory cells.
In a conventional NAND EEPROM or AND EEPROM, in order to decrease the resistances of the select gate lines of select gate transistors, interconnections (so-called backside sub wires) lower in resistance than the select gate lines are arranged on an interconnection layer located above an interconnection layer on which the select gate lines are arranged, and contact areas (so-called shunt areas) between the select gate lines and the backside sub wires are arranged at predetermined intervals.
According to the prior art, therefore, the memory cell array region expands due to such backside sub wires and shut areas, and it is difficult to reduce the chip area.
This problem will be described in detail below.
FIG. 41 is an equivalent circuit of a cell unit of a conventional NAND EEPROM. FIG. 42 is an equivalent circuit of a cell unit of a conventional AND EEPROM.
As shown in FIG. 41, a cell unit 45 of a NAND EEPROM is comprised of a NAND string constituted by plural (16 in this case) series-connected memory cells M0, M1, . . . , M15 and two select gate transistors S1 and S2 respectively connected to the two ends of the NAND string.
As shown in FIG. 42, a cell unit 45 of an AND EEPROM is comprised of plural (16 in this case) memory cells M0, M1, . . . , M15 connected in parallel with each other between nodes A and B, and two select gate transistors S1 and S2 respectively connected to the two nodes A and B.
In either of the cell units 45 shown in FIGS. 41 and 42, plural (16 in this case) control gate lines (word lines) WL0, WL1, . . . , WL15 are connected, and one or more (two in this case) select gate lines (block select lines) SSL and GSL are connected. Note that at least one select gate line is connected to the cell unit 45, and preferably extends in the same direction as the direction (row direction) in which the control gate lines WL0, WL1, . . . , WL15 extend for the sake of increasing the packing density of memory cells.
A bit line (data transfer line) BL extends in a direction (column direction) perpendicular to the direction in which the word lines (data select lines) WL0, WL1, . . . , WL15 extend. The memory cells M0, M1, . . . , M15 are respectively placed at the intersections of the bit line BL and the word lines WL0, WL1, , WL15, and independently allow writes and reads of digital bit data.
In this case, a memory cell includes a floating gate electrode (charge storing layer). The value of digital bit data is determined by the amount of charge in the floating gate electrode. Plural cell units are arranged in the row and column directions, thus forming a memory cell matrix. Note that a set of plural cell units arranged in the row direction is called a block.
In a large-scale memory in which memory cells are mounted at a high packing density, interconnections are thin and long, and hence it is important to decrease their resistances. Since the control gate lines (word lines) WL0, WL1, . . . , WL15 are the thinnest interconnections in the chip, various techniques have been studied to decrease their resistances.
For example, a technique of making the control gate lines WL0, WL1, . . . , WL15 have a multilayer structure consisting of impurity-doped conductive polysilicon and a low-resistance material is known well. As this low-resistance material, for example, a metal silicide such as WSi, CoSi, NiSi, or TiSi or a metal such as Ta or W is used.
In general, the select gate lines SSL and GSL of the select gate transistors are arranged on an interconnection layer different from an interconnection layer on which the control gate lines WL0, WL1, . . . , WL15 of the memory cells are arranged.
In this case, if, for example, the select gate lines SSL and GSL are formed to have a multilayer structure consisting of impurity-doped conductive polysilicon and a low-resistance material, a decrease in the resistance of the select gate lines SSL and GSL can be attained. However, since the interconnection layer on which the select gate lines SSL and GSL are arranged differs from the interconnection layer on which the control gate lines WL0, WL1, . . . , WL15 are arranged, photolithography and a process (RIE) are independently required on the select gate transistor side and the memory cell side.
As a consequence, misalignment occurs between the select gate lines SSL and GSL and the control gate lines WL0, WL1, . . . , WL15, and hence some margin must be ensured in consideration of the misalignment. The chip area increased by this margin.
If the select gate lines SSL and GSL are arranged on the same interconnection layer as the interconnection layer on which the floating gate electrodes (charge storing layers) of the memory cells are arranged, the problem of an increase in chip area due to the above alignment can be prevented.
If, therefore, the select gate lines SSL and GSL and floating gate electrodes (charge storing layers) are arranged on the same interconnection layer and made to have a multilayer structure consisting of impurity-doped conductive polysilicon and a low-resistance material (metal silicide, metal, or the like), a decrease in the resistance of the select gate lines SSL and GSL can be attained, and photolithography and a process (RIE) can be commonly performed on the select gate transistor side and the memory cell side. This makes it possible to prevent the problem of an increase in chip area.
In this case, however, a problem arises in terms of the breakdown voltage of the insulating films between the control gate electrodes and floating gate electrodes of the memory cells.
It is known that the breakdown voltage of the insulating film between the control gate electrode and floating gate electrode of each memory cell greatly decreases as atoms of a metal such as W, Ni, or Ti enter the floating gate electrode. If, therefore, the floating gate electrode has a multilayer structure consisting of impurity-doped conductive polysilicon and a low-resistance material (metal silicide, metal, or the like), the breakdown of the insulating film between the control gate electrode and floating gate electrode of the memory cell decreases, resulting in difficulty in stabilizing the operation of the memory.
When the select gate lines SSL and GSL and floating gate electrodes (charge storing layers) are to be arranged on the same interconnection layer, conductive polysilicon doped with P, As, or B must be used for the select gate lines SSL and GSL and floating gate electrodes. As a result, the resistance of the resultant interconnections become higher than that of the interconnections made of a metal or metal silicide.
When, therefore, the select gate lines SSL and GSL and floating gate electrodes are to be arranged on the same interconnection layer, a technique (stitch interconnection technique) is used, in which so-called backside sub wires are arranged on an interconnection layer located above the interconnection layer on which the select gate lines SSL and GSL are arranged, and the select gate lines SSL and GSL are brought into contact with the backside sub wires every 10 to 1,000 cell units.
In this technique, however, contact areas (shunt areas) for the select gate lines and backside sub wires are required, and hence the chip area increases by the contact areas.
As described above, in a conventional semiconductor memory having a cell unit constituted by plural memory cells connected in series or in parallel, photolithography and a process must be independently performed on the memory cell side and the select gate transistor side, and contact areas for the select gate lines and the backside sub wires located thereabove must be formed, resulting in an increase in chip area.
(1) It is an object of the present invention to provide a semiconductor memory (Ferroelectric RAM) which is excellent at micropatterning memory cells, reducing chip size, decreasing write/read voltages, reducing power consumption, and simplifying a manufacturing process, and can attain high-speed operation and high reliability.
In order to achieve the above object, a semiconductor memory according to the present invention has a cell unit constituted by plural series-connected transistors, a bit line connected to one end of the cell unit, and a source line connected to the other end of the cell unit. Each transistor has substantially the same structure and the function of storing data in a nonvolatile manner. Of the plural transistors, one transistor nearest to the bit line and one transistor nearest to the source line are used as select gate transistors. The transistors other than the transistors used as the select gate transistors are used as memory cells.
A semiconductor memory according to the present invention has a cell unit constituted by plural series-connected MFSFETS having substantially the same structure, a bit line connected to one end of the cell unit, and a source line connected to the other end of the cell unit. Of the plural MFSFETS, one MFSFET nearest to the bit line and one MFSFET nearest to the source line are used as select gate transistors, and the MFSFETs other than the MFSFETS used as the select gate transistors are used as memory cells.
(2) It is an object of the present invention to provide a device structure and memory cell layout, which can realize a high-density cell layout and reductions in the resistances of select gate lines and control gate lines and eliminate the necessity to independently perform photolithography and a process on the memory cell side and the select gate transistor side and to form backside sub wires by forming the select gate lines and control gate lines on the same interconnection layer and making them have a multilayer structure consisting of conductive polysilicon and a low-resistance material.
In order to achieve the above object, a semiconductor memory according to the present invention has plural memory cells connected in series or parallel between first and second nodes, and select gate transistors connected between the first node and a third node. Each of plural memory cells and select gate transistors has a charge storing layer. The charge storing layer of each of the plural memory cells is made of the same material as that for each of the select gate transistors, and has the same thickness as that thereof.
In addition, a semiconductor memory according to the present invention has a memory cell and a select gate transistor connected between the memory cell and a bit line or source line. Both the memory cell and the semiconductor have charge storing layers, and the charge storing layer of the memory cell is made of the same material as that for the select gate transistor and has the same thickness as that thereof.
(3) Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.